UniTAP.dev.modules.dut_tests.dut_default_params.usbc_electrical_tests

Class UsbcElTestDutCaps describes DUT capabilities flags and allows settings values.

• DUT Support DisplayPort Alternate mode support_dp_alt_mode.
• DUT can act as a power source can_act_power_source
• DUT can act as a power sink cab_act_power_sink.
• DUT does not support PD Contract not_support_pd_contract.

Class DpElectricalTestParam describes parameters for DP electrical tests.

• Test timeout, in milliseconds timeout.
• Defines DUT capabilities dut_caps type UsbcElTestDutCaps.
• Defines the time period for USB Type-C re-plug simulation 'disconnected' state re_plug_time.
• Defines the time period that the TE will wait for DUT to complete power contract negotiation attach_timeout.
• Defines Power Contract timeout, in milliseconds pwr_contract_timeout.
• Defines the low limit for the voltage window when power sink current is 0.5A or 0.9A cc_low_voltage_1.
• Defines the high limit for the voltage window when power sink current is 0.5A or 0.9A cc_high_voltage_1.
• Defines the low limit for the voltage window when power sink current is 1.5A cc_low_voltage_2.
• Defines the high limit for the voltage window when power sink current is 1.5A cc_high_voltage_2.
• Defines the low limit for the voltage window when power sink current is 3.0A cc_low_voltage_3.
• Defines the high limit for the voltage window when power sink current is 3.0A cc_high_voltage_3.
• Defines the low limit for the Vcon voltage window vconn_low_voltage.
• Defines the high limit for the Vcon voltage window vconn_high_voltage.
• Defines the timeout the TE will wait for the DUT to enter into DisplayPort alternate mode dp_alt_mode_timeout.
• Defines the low voltage limit for the positive DP AUX line when idle aux_positive_idle_low_voltage.
• Defines the high voltage limit for the positive DP AUX line when idle aux_positive_idle_high_voltage.
• Defines the low voltage limit for the negative DP AUX line when idle aux_negative_idle_low_voltage.
• Defines the high voltage limit for the negative DP AUX line when idle aux_negative_idle_high_voltage.
• Defines the low limit for Vbus voltage window. The limit is defined in millivolts (mV) vbus_low_voltage.
• Defines the high limit for Vbus voltage window. The limit is defined in millivolts (mV) vbus_high_voltage.
• Defines the highest allowed deviation between maximum and minimum currents measured from the individual Vbus pins as per-mill (‰) of total measured current. This means that if the total measured current is 3000mA, and the setting 100, the maximum difference that is allowed between maximum and minimum currents is 300mA vbus_current_max.
• Defines the highest allowed deviation between maximum and minimum currents measured from the individual GND pins as per-mill (‰) of total measured current gnd_current_max.
• Defines delay from end of power contract negotiation to voltage / current measurements power_measure_delay.
• Defines the minimum current, in mA, that a Power Sink DUT must use in order to pass the test min_dut_current.
• Delay after load resistor on, milliseconds. This helps to skip transient processes resistor_on_delay.
• Delay for measure CC lines voltage after DUT plug detection, milliseconds cc_measure_delay.