# UniTAP.dev.ports.modules.fec.fec_tx

class FecTx:

Class `FecTx` allows working with FEC functionality from Source (TX - transmitter) side. You can:

- Check enabled FEC or not `is_enabled`.
- Check state that FEC is prefers after link training `is_prefer_after_lt`.
- Enable/Disable FEC `enable`.
- Enable/Disable intent FEC `enable_intent`.
- Enable/Disable calculating sum of errors `aggregate_errors`.
- Get error counters `get_error_counters`.
- Clear all errors `clear`.

FecTx( port_io: UniTAP.libs.lib_tsi.tsi_io.PortIO, dpcd: UniTAP.dev.ports.modules.dpcd.dpcd.DPCDRegisters)
def is_enabled(self) -> bool:

Returns status of FEC, is enabled or not.

###### Returns:

> object of `bool` type.

def is_prefer_after_lt(self) -> bool:

Check state that FEC is prefers after link training.

###### Returns:

> object of `bool` type.

def enable(self, enable: bool):

Enable/Disable FEC.

###### Arguments:

- enable (bool) - enable (True) or disable (False)

def enable_intent(self, enable: bool):

Enable/Disable intent FEC.

###### Arguments:

- enable (bool) - enable (True) or disable (False)

def aggregate_errors(self, enable: bool):

Enable/Disable calculating sum of errors.

###### Arguments:

- enable (bool) - enable (True) or disable (False)

def generate_errors( self, error_type: Union[ UniTAP.dev.ports.modules.fec.fec_shared.FECErrorType8b10b , UniTAP.dev.ports.modules.fec.fec_shared.FECErrorType128b132b ], lane: list, ms: int = 100):

Generate FEC errors.

###### Arguments:

- error_type (Union[`FECErrorType8b10b`, `FECErrorType128b132b`])
- lane (list)
- ms (int) - time in m seconds

def get_error_counters(self) -> UniTAP.dev.ports.modules.fec.fec_shared.FECCounters:

Get current error counters.

###### Returns:

> object of `FECCounters` type

def clear(self):

Clear all errors.