# UniTAP.dev.ports.modules.link.dp.link_rx_types

class LinkCapabilities:

Class `LinkCapabilities` describes capabilities of DP link.

max_lane
bit_rate
dp_128_132_bitrates
override_10g
old_dp_2_0_lt
force_cable_status_to_plugged
mst
ss_sbm
fec
tps4
tps3
dsc
mst_sink_count
class LinkEDPCapabilities:

Class `LinkEDPCapabilities` describes capabilities of eDP link.

max_lane
eDp_cur_rate
eDp_supported_rates
eDp_aux_preamble
eDp_support
class CableCapabilitiesEnum(enum.IntEnum):

Enum where members are also (and must be) ints

Unknown = <CableCapabilitiesEnum.Unknown: 0>
DP40 = <CableCapabilitiesEnum.DP40: 1>
DP54 = <CableCapabilitiesEnum.DP54: 2>
DP80 = <CableCapabilitiesEnum.DP80: 3>

##### Inherited Members

enum.Enum
  name
  value
builtins.int
  conjugate
  bit_length
  bit_count
  to_bytes
  from_bytes
  as_integer_ratio
  real
  imag
  numerator
  denominator

class RoutedLTConfig:

Class `RoutedLTConfig` describes configuration fields for Routed LinkTraining.

is128b132b: bool
is_old_dp20_lt: bool
vs: int
pe: int
ffe: int
link_bw: int
lane_count: int
def int_value(self) -> int:
class RoutedLTStatus:
RoutedLTStatus( enabled: bool, dp20_old_lt: bool, state: int, success: bool, step: int)
enabled
dp20_old_lt
state
success
step