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更新UCD-API库及文档

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This commit is contained in:
xinzhu.yin
2026-07-02 17:16:18 +08:00
parent a500751d85
commit 9fa811a9eb
290 changed files with 9558 additions and 2306 deletions
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16
UniTAP/dev/ports/modules/fec/fec_rx.py
View File

@@ -1,4 +1,6 @@
from UniTAP.libs.lib_tsi.tsi import *
from ctypes import c_int
import UniTAP.libs.lib_tsi.tsi_types as ci
from UniTAP.libs.lib_tsi.tsi_io import PortIO
from .fec_shared import FECCounters
@@ -27,7 +29,7 @@ class FecRx:
Returns:
object of `bool` type.
"""
result = self.__io.get(TSI_DPRX_FEC_STATUS_R, c_int)
result = self.__io.get(ci.TSI_DPRX_FEC_STATUS_R, c_int)
status_fec = ((result[1] & 0x1) != 0)
return bool(status_fec)
@@ -38,7 +40,7 @@ class FecRx:
Returns:
object of `bool` type.
"""
result = self.__io.get(TSI_DPRX_FEC_CTRL, c_int)
result = self.__io.get(ci.TSI_DPRX_FEC_CTRL, c_int)
enabled_fec = (result[1] & 0x1) != 0
return enabled_fec
@@ -50,7 +52,7 @@ class FecRx:
enable (bool) - enable (True) or disable (False)
"""
val = 0x1 if enable else 0x0
self.__io.set(TSI_DPRX_FEC_CTRL, val)
self.__io.set(ci.TSI_DPRX_FEC_CTRL, val)
def aggregate_errors(self, enable: bool):
"""
@@ -59,7 +61,7 @@ class FecRx:
Args:
enable (bool) - enable (True) or disable (False)
"""
result = self.__io.get(TSI_DPRX_FEC_CONTROL, c_int)
result = self.__io.get(ci.TSI_DPRX_FEC_CONTROL, c_int)
val = result[1]
if enable:
val |= 0x2
@@ -67,7 +69,7 @@ class FecRx:
else:
val &= ~0x2
self.__aggregate_error = 0
self.__io.set(TSI_DPRX_FEC_CONTROL, val)
self.__io.set(ci.TSI_DPRX_FEC_CONTROL, val)
def get_error_counters(self) -> FECCounters:
"""
@@ -78,7 +80,7 @@ class FecRx:
object of `FECCounters` type
"""
result = FECCounters()
lane_count = self.__io.get(TSI_R_DPRX_LINK_LANE_COUNT, c_int)[1]
lane_count = self.__io.get(ci.TSI_R_DPRX_LINK_LANE_COUNT, c_int)[1]
if lane_count == 4:
lane_count += 1 if self.__aggregate_error else 0

51
UniTAP/dev/ports/modules/fec/fec_tx.py
View File

@@ -1,5 +1,8 @@
from UniTAP.libs.lib_tsi.tsi import *
from ctypes import c_int, c_uint32
from UniTAP.libs.lib_tsi.tsi_io import PortIO
import UniTAP.libs.lib_tsi.tsi_private_types as p_ci
import UniTAP.libs.lib_tsi.tsi_types as ci
from .fec_shared import FECCounters, FECErrorType8b10b, FECErrorType128b132b
from UniTAP.dev.ports.modules.dpcd.dpcd import DPCDRegisters
@@ -29,7 +32,7 @@ class FecTx:
Returns:
object of `bool` type.
"""
result = self.__io.get(TSI_DPTX_FEC_STATUS_R, c_int)
result = self.__io.get(ci.TSI_DPTX_FEC_STATUS_R, c_int)
status_fec = ((result[1] & 0x1) != 0)
return bool(status_fec)
@@ -40,7 +43,7 @@ class FecTx:
Returns:
object of `bool` type.
"""
result = self.__io.get(TSI_DPTX_FEC_CTRL, c_int)
result = self.__io.get(ci.TSI_DPTX_FEC_CTRL, c_int)
enabled_fec = (result[1] & 0x2) != 0
return enabled_fec
@@ -51,10 +54,10 @@ class FecTx:
Args:
enable (bool) - enable (True) or disable (False)
"""
result = self.__io.get(TSI_DPTX_FEC_CTRL, c_int)
result = self.__io.get(ci.TSI_DPTX_FEC_CTRL, c_int)
val = result[1]
val |= 0x8 if enable else 0x10
self.__io.set(TSI_DPTX_FEC_CTRL, val)
self.__io.set(ci.TSI_DPTX_FEC_CTRL, val)
def enable_intent(self, enable: bool):
"""
@@ -63,10 +66,10 @@ class FecTx:
Args:
enable (bool) - enable (True) or disable (False)
"""
result = self.__io.get(TSI_DPTX_FEC_CTRL, c_int)
result = self.__io.get(ci.TSI_DPTX_FEC_CTRL, c_int)
val = result[1]
val |= 1 if enable else 4
self.__io.set(TSI_DPTX_FEC_CTRL, val)
self.__io.set(ci.TSI_DPTX_FEC_CTRL, val)
def aggregate_errors(self, enable: bool):
"""
@@ -75,7 +78,7 @@ class FecTx:
Args:
enable (bool) - enable (True) or disable (False)
"""
result = self.__io.get(TSI_DPTX_FEC_CONTROL, c_int)
result = self.__io.get(ci.TSI_DPTX_FEC_CONTROL, c_int)
val = result[1]
if enable:
val |= 0x40
@@ -83,7 +86,7 @@ class FecTx:
else:
val &= ~0x40
self.__aggregate_error = 0
self.__io.set(TSI_DPTX_FEC_CONTROL, val)
self.__io.set(ci.TSI_DPTX_FEC_CONTROL, val)
def generate_errors(self, error_type: Union[FECErrorType8b10b, FECErrorType128b132b], lane: list, ms: int = 100):
"""
@@ -94,8 +97,8 @@ class FecTx:
lane (list)
ms (int) - time in m seconds
"""
result, status = self.__io.get(TSI_DPTX_LINK_MODE_R, c_int)
resut, hw_caps, size = self.__io.get(TSI_DPTX_HW_CAPS_R, c_uint32, 4)
result, status = self.__io.get(ci.TSI_DPTX_LINK_MODE_R, c_int)
resut, hw_caps, size = self.__io.get(ci.TSI_DPTX_HW_CAPS_R, c_uint32, 4)
if status == 0:
if isinstance(error_type, FECErrorType128b132b):
assert False, "This device doesn't support 128b/132b" if (hw_caps[1] & 0x7) == 0 else "Change link mode!"
@@ -109,24 +112,24 @@ class FecTx:
delay = ms * 100
self.__io.set(TSI_MLEG_CONTROL, 0)
nl = self.__io.get(TSI_R_DPTX_LINK_STATUS_LANE_COUNT, c_uint32)[1]
self.__io.set(p_ci.TSI_MLEG_CONTROL, 0)
nl = self.__io.get(ci.TSI_R_DPTX_LINK_STATUS_LANE_COUNT, c_uint32)[1]
self.__io.set(TSI_MLEG_SYMBOL_REPLACE_A, 0x00010000)
self.__io.set(TSI_MLEG_SYMBOL_REPLACE_MASK_A, 0x00010001)
self.__io.set(TSI_MLEG_SYMBOL_REPLACE_B, 0x00000001)
self.__io.set(TSI_MLEG_SYMBOL_REPLACE_MASK_B, 0x00010001)
self.__io.set(p_ci.TSI_MLEG_SYMBOL_REPLACE_A, 0x00010000)
self.__io.set(p_ci.TSI_MLEG_SYMBOL_REPLACE_MASK_A, 0x00010001)
self.__io.set(p_ci.TSI_MLEG_SYMBOL_REPLACE_B, 0x00000001)
self.__io.set(p_ci.TSI_MLEG_SYMBOL_REPLACE_MASK_B, 0x00010001)
self.__io.set(TSI_MLEG_DELAY_COUNTER, delay)
self.__io.set(p_ci.TSI_MLEG_DELAY_COUNTER, delay)
n = lane[0] << 16
self.__io.set(TSI_MLEG_LANE0_REPLACE_COUNTERS, n)
self.__io.set(p_ci.TSI_MLEG_LANE0_REPLACE_COUNTERS, n)
n = lane[1] << 16
self.__io.set(TSI_MLEG_LANE1_REPLACE_COUNTERS, n)
self.__io.set(p_ci.TSI_MLEG_LANE1_REPLACE_COUNTERS, n)
n = lane[2] << 16
self.__io.set(TSI_MLEG_LANE2_REPLACE_COUNTERS, n)
self.__io.set(p_ci.TSI_MLEG_LANE2_REPLACE_COUNTERS, n)
n = lane[3] << 16
self.__io.set(TSI_MLEG_LANE3_REPLACE_COUNTERS, n)
self.__io.set(p_ci.TSI_MLEG_LANE3_REPLACE_COUNTERS, n)
ctrl = 0
ctrl |= (error_type.value << 16)
@@ -144,7 +147,7 @@ class FecTx:
if lane[3]:
ctrl |= (1 << 3)
self.__io.set(TSI_MLEG_CONTROL, ctrl)
self.__io.set(p_ci.TSI_MLEG_CONTROL, ctrl)
def get_error_counters(self) -> FECCounters:
"""
@@ -154,7 +157,7 @@ class FecTx:
object of `FECCounters` type
"""
result = FECCounters()
lane_count = self.__io.get(TSI_R_DPTX_LINK_STATUS_LANE_COUNT, c_uint32)[1]
lane_count = self.__io.get(ci.TSI_R_DPTX_LINK_STATUS_LANE_COUNT, c_uint32)[1]
if lane_count == 4:
lane_count += 1 if self.__aggregate_error else 0