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更新UCD-API库及文档

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This commit is contained in:
xinzhu.yin
2026-07-02 17:16:18 +08:00
parent a500751d85
commit 9fa811a9eb
290 changed files with 9558 additions and 2306 deletions
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16
UniTAP/dev/ports/modules/fec/fec_rx.py
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@@ -1,4 +1,6 @@
from UniTAP.libs.lib_tsi.tsi import *
from ctypes import c_int
import UniTAP.libs.lib_tsi.tsi_types as ci
from UniTAP.libs.lib_tsi.tsi_io import PortIO
from .fec_shared import FECCounters
@@ -27,7 +29,7 @@ class FecRx:
Returns:
object of `bool` type.
"""
result = self.__io.get(TSI_DPRX_FEC_STATUS_R, c_int)
result = self.__io.get(ci.TSI_DPRX_FEC_STATUS_R, c_int)
status_fec = ((result[1] & 0x1) != 0)
return bool(status_fec)
@@ -38,7 +40,7 @@ class FecRx:
Returns:
object of `bool` type.
"""
result = self.__io.get(TSI_DPRX_FEC_CTRL, c_int)
result = self.__io.get(ci.TSI_DPRX_FEC_CTRL, c_int)
enabled_fec = (result[1] & 0x1) != 0
return enabled_fec
@@ -50,7 +52,7 @@ class FecRx:
enable (bool) - enable (True) or disable (False)
"""
val = 0x1 if enable else 0x0
self.__io.set(TSI_DPRX_FEC_CTRL, val)
self.__io.set(ci.TSI_DPRX_FEC_CTRL, val)
def aggregate_errors(self, enable: bool):
"""
@@ -59,7 +61,7 @@ class FecRx:
Args:
enable (bool) - enable (True) or disable (False)
"""
result = self.__io.get(TSI_DPRX_FEC_CONTROL, c_int)
result = self.__io.get(ci.TSI_DPRX_FEC_CONTROL, c_int)
val = result[1]
if enable:
val |= 0x2
@@ -67,7 +69,7 @@ class FecRx:
else:
val &= ~0x2
self.__aggregate_error = 0
self.__io.set(TSI_DPRX_FEC_CONTROL, val)
self.__io.set(ci.TSI_DPRX_FEC_CONTROL, val)
def get_error_counters(self) -> FECCounters:
"""
@@ -78,7 +80,7 @@ class FecRx:
object of `FECCounters` type
"""
result = FECCounters()
lane_count = self.__io.get(TSI_R_DPRX_LINK_LANE_COUNT, c_int)[1]
lane_count = self.__io.get(ci.TSI_R_DPRX_LINK_LANE_COUNT, c_int)[1]
if lane_count == 4:
lane_count += 1 if self.__aggregate_error else 0