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更新UCD-API库及文档

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This commit is contained in:
xinzhu.yin
2026-07-02 17:16:18 +08:00
parent a500751d85
commit 9fa811a9eb
290 changed files with 9558 additions and 2306 deletions
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6
UniTAP/dev/ports/modules/link/hdmi/arc_rx.py
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@@ -1,6 +1,6 @@
from UniTAP.libs.lib_tsi.tsi_io import PortIO
from enum import IntEnum
from UniTAP.libs.lib_tsi.tsi_types import TSI_ARC_CONTROL_W, TSI_HDRX_ARC_STATUS_R
import UniTAP.libs.lib_tsi.tsi_types as ci
from ctypes import c_uint32
@@ -44,10 +44,10 @@ class ArcRx:
self.__single_mode = True
def __read_arc_status(self) -> int:
return self.__io.get(TSI_HDRX_ARC_STATUS_R, c_uint32)[1]
return self.__io.get(ci.TSI_HDRX_ARC_STATUS_R, c_uint32)[1]
def __write_arc(self, value: int):
self.__io.set(TSI_ARC_CONTROL_W, value, c_uint32)
self.__io.set(ci.TSI_ARC_CONTROL_W, value, c_uint32)
@property
def supported(self) -> bool:

12
UniTAP/dev/ports/modules/link/hdmi/frl_caps_rx.py
View File

@@ -1,6 +1,6 @@
from UniTAP.libs.lib_tsi.tsi_io import PortIO
from .types import FrlMode, LtpLanesPattern, FrlCaps, LtpPattern, _update_frl_values, _update_ltp_pattern_values
from UniTAP.libs.lib_tsi.tsi_types import TSI_HDRX_FRL_CAPABILITY, TSI_HDRX_FRL_PATTERN, TSI_HDRX_LINK_STATUS_R
import UniTAP.libs.lib_tsi.tsi_types as ci
from ctypes import c_uint32
@@ -19,16 +19,16 @@ class FrlControlRx:
self.__ltp_additional = LtpLanesPattern()
def __read_caps(self) -> int:
return self.__io.get(TSI_HDRX_FRL_CAPABILITY, c_uint32)[1]
return self.__io.get(ci.TSI_HDRX_FRL_CAPABILITY, c_uint32)[1]
def __write_caps(self, value: int):
self.__io.set(TSI_HDRX_FRL_CAPABILITY, value, c_uint32)
self.__io.set(ci.TSI_HDRX_FRL_CAPABILITY, value, c_uint32)
def __read_frl_pattern(self) -> int:
return self.__io.get(TSI_HDRX_FRL_PATTERN, c_uint32)[1]
return self.__io.get(ci.TSI_HDRX_FRL_PATTERN, c_uint32)[1]
def __write_frl_pattern(self, value: int):
self.__io.set(TSI_HDRX_FRL_PATTERN, value, c_uint32)
self.__io.set(ci.TSI_HDRX_FRL_PATTERN, value, c_uint32)
@property
def frl_mode(self) -> FrlMode:
@@ -130,7 +130,7 @@ class FrlControlRx:
"""
DO re train.
"""
self.__io.set(TSI_HDRX_LINK_STATUS_R, 0x1c0000, c_uint32)
self.__io.set(ci.TSI_HDRX_LINK_STATUS_R, 0x1c0000, c_uint32)
def __str__(self):
return f"FRL Mode: {self.frl_mode.name}\n" \

17
UniTAP/dev/ports/modules/link/hdmi/frl_control_tx.py
View File

@@ -1,7 +1,6 @@
from UniTAP.libs.lib_tsi.tsi_io import PortIO
from .types import FrlMode, LtpLanesPattern, FrlCaps, _update_frl_values, _update_ltp_pattern_values
from UniTAP.libs.lib_tsi.tsi_types import TSI_HDTX_FRL_CAPABILITY, TSI_HDTX_FRL_PATTERN_R, TSI_HDTX_FRL_TIMERS, \
TSI_HDTX_SINK_FEATURE_W, TSI_HDTX_FRL_STATUS_R
import UniTAP.libs.lib_tsi.tsi_types as ci
from ctypes import c_uint32
@@ -197,19 +196,19 @@ class FrlControlTx:
self.__ltp_additional = LtpLanesPattern()
def __read_caps(self) -> int:
return self.__io.get(TSI_HDTX_FRL_CAPABILITY, c_uint32)[1]
return self.__io.get(ci.TSI_HDTX_FRL_CAPABILITY, c_uint32)[1]
def __write_caps(self, value: int):
self.__io.set(TSI_HDTX_FRL_CAPABILITY, value, c_uint32)
self.__io.set(ci.TSI_HDTX_FRL_CAPABILITY, value, c_uint32)
def __read_frl_timers(self) -> int:
return self.__io.get(TSI_HDTX_FRL_TIMERS, c_uint32)[1]
return self.__io.get(ci.TSI_HDTX_FRL_TIMERS, c_uint32)[1]
def __write_frl_timers(self, value: int):
self.__io.set(TSI_HDTX_FRL_TIMERS, value, c_uint32)
self.__io.set(ci.TSI_HDTX_FRL_TIMERS, value, c_uint32)
def __read_frl_patterns(self) -> int:
return self.__io.get(TSI_HDTX_FRL_PATTERN_R, c_uint32)[1]
return self.__io.get(ci.TSI_HDTX_FRL_PATTERN_R, c_uint32)[1]
@property
def ltp_pattern(self) -> LtpLanesPattern:
@@ -243,7 +242,7 @@ class FrlControlTx:
Returns:
object of `FrlCaps` type
"""
_update_frl_values(self.__frl_caps, self.__io.get(TSI_HDTX_FRL_STATUS_R, c_uint32)[1])
_update_frl_values(self.__frl_caps, self.__io.get(ci.TSI_HDTX_FRL_STATUS_R, c_uint32)[1])
return self.__frl_caps
@property
@@ -345,7 +344,7 @@ class FrlControlTx:
"""
Do link training.
"""
self.__io.set(TSI_HDTX_SINK_FEATURE_W, 5, c_uint32)
self.__io.set(ci.TSI_HDTX_SINK_FEATURE_W, 5, c_uint32)
@staticmethod
def __update_values(ffe_max: FfeMax, value: int):

6
UniTAP/dev/ports/modules/link/hdmi/link.py
View File

@@ -9,7 +9,7 @@ from .status_tx import StatusTx, HdmiModeTx
from .capabilities import HdmiCapabilities
from .frl_control_tx import FrlControlTx
from .frl_caps_rx import FrlControlRx
from UniTAP.libs.lib_tsi.tsi_types import TSI_HDTX_CAPABILITY_R, TSI_HDRX_CAPABILITY_R
import UniTAP.libs.lib_tsi.tsi_types as ci
from typing import Optional
@@ -25,7 +25,7 @@ class HdmiLinkTx:
self.__tmds = TmdsTx(self.__io)
self.__status = StatusTx(self.__io)
self.__frl = FrlControlTx(self.__io)
self.__caps = HdmiCapabilities(TSI_HDTX_CAPABILITY_R, self.__io)
self.__caps = HdmiCapabilities(ci.TSI_HDTX_CAPABILITY_R, self.__io)
@property
def tmds(self) -> Optional[TmdsTx]:
@@ -96,7 +96,7 @@ class HdmiLinkRx:
self.__status = StatusRx(self.__io)
self.__frl = FrlControlRx(self.__io)
self.__arc = ArcRx(self.__io)
self.__caps = HdmiCapabilities(TSI_HDRX_CAPABILITY_R, self.__io)
self.__caps = HdmiCapabilities(ci.TSI_HDRX_CAPABILITY_R, self.__io)
@property
def tmds(self) -> Optional[TmdsRx]:

26
UniTAP/dev/ports/modules/link/hdmi/status_rx.py
View File

@@ -2,9 +2,7 @@ import time
from UniTAP.libs.lib_tsi.tsi_io import PortIO
from .types import HdmiModeRx, FrlMode, _update_error_counters_rx
from UniTAP.libs.lib_tsi.tsi_types import TSI_HDRX_BEHAVIOR, TSI_HDRX_LANES_ERR_COUNTERS_R, TSI_HDRX_HPD_STATUS_R,\
TSI_HDRX_FRL_CAPABILITY, TSI_HDRX_LINK_STATUS_R, TSI_HDRX_HPD_CONTROL_W, TSI_HDRX_VIDEO_MODE_R, \
TSI_VIDCAP_SIGNAL_CRC_R, TSI_SUCCESS
import UniTAP.libs.lib_tsi.tsi_types as ci
from ctypes import c_uint8, c_uint32, c_uint64
from UniTAP.utils.function_wrapper import function_scheduler
from .types import _hdmi_vm_info_to_video_mode, HdmiVideoModeInfo
@@ -25,7 +23,7 @@ class StatusRx:
self.__io = port_io
def __frl_status(self) -> FrlMode:
return FrlMode(self.__io.get(TSI_HDRX_FRL_CAPABILITY, c_uint32)[1] & 0xF)
return FrlMode(self.__io.get(ci.TSI_HDRX_FRL_CAPABILITY, c_uint32)[1] & 0xF)
@property
def hdmi_mode(self) -> HdmiModeRx:
@@ -35,7 +33,7 @@ class StatusRx:
Returns:
object of `HdmiModeRx` type
"""
return HdmiModeRx(self.__io.get(TSI_HDRX_BEHAVIOR, c_uint32)[1])
return HdmiModeRx(self.__io.get(ci.TSI_HDRX_BEHAVIOR, c_uint32)[1])
@hdmi_mode.setter
def hdmi_mode(self, hdmi_mode: HdmiModeRx):
@@ -45,7 +43,7 @@ class StatusRx:
Args:
hdmi_mode (HdmiModeRx)
"""
self.__io.set(TSI_HDRX_BEHAVIOR, hdmi_mode.value, c_uint32)
self.__io.set(ci.TSI_HDRX_BEHAVIOR, hdmi_mode.value, c_uint32)
@property
def error_counters(self) -> list:
@@ -55,7 +53,7 @@ class StatusRx:
Returns:
object of list type
"""
return _update_error_counters_rx(self.__io.get(TSI_HDRX_LANES_ERR_COUNTERS_R, c_uint64)[1])
return _update_error_counters_rx(self.__io.get(ci.TSI_HDRX_LANES_ERR_COUNTERS_R, c_uint64)[1])
def set_assert_state(self, asserted: bool = True):
"""
@@ -64,7 +62,7 @@ class StatusRx:
Args:
asserted (bool)
"""
self.__io.set(TSI_HDRX_HPD_CONTROL_W, int(asserted), c_uint32)
self.__io.set(ci.TSI_HDRX_HPD_CONTROL_W, int(asserted), c_uint32)
@property
def channel_lock(self) -> list:
@@ -74,7 +72,7 @@ class StatusRx:
Returns:
object of list type
"""
return self.__update_channel_lock(self.__io.get(TSI_HDRX_LINK_STATUS_R, c_uint32)[1], self.hdmi_mode)
return self.__update_channel_lock(self.__io.get(ci.TSI_HDRX_LINK_STATUS_R, c_uint32)[1], self.hdmi_mode)
@staticmethod
def __update_channel_lock(value: int, mode: HdmiModeRx) -> list:
@@ -99,11 +97,11 @@ class StatusRx:
Returns:
object of bool type
"""
return (self.__io.get(TSI_HDRX_HPD_STATUS_R, c_uint32)[1] & 0x1) != 0
return (self.__io.get(ci.TSI_HDRX_HPD_STATUS_R, c_uint32)[1] & 0x1) != 0
def __check_video(self) -> bool:
def is_msa_available(io):
result, msa_info, size = io.get(TSI_HDRX_VIDEO_MODE_R, HdmiVideoMode, 4)
result, msa_info, size = io.get(ci.TSI_HDRX_VIDEO_MODE_R, HdmiVideoMode, 4)
return result > 0
return function_scheduler(is_msa_available, self.__io, interval=5, timeout=10)
@@ -125,7 +123,7 @@ class StatusRx:
time.sleep(1)
result, hdmi_video_mode_info, size = self.__io.get(TSI_HDRX_VIDEO_MODE_R, HdmiVideoMode, 4)
result, hdmi_video_mode_info, size = self.__io.get(ci.TSI_HDRX_VIDEO_MODE_R, HdmiVideoMode, 4)
# TODO - Size temporary will be equal 1
size = 1
@@ -133,8 +131,8 @@ class StatusRx:
if 0 <= stream_index < size:
stream_status.video_mode = _hdmi_vm_info_to_video_mode(HdmiVideoModeInfo(hdmi_video_mode_info
[stream_index]))
result = self.__io.get(TSI_VIDCAP_SIGNAL_CRC_R, data_type=c_uint8, data_count=6)
if result[0] >= TSI_SUCCESS:
result = self.__io.get(ci.TSI_VIDCAP_SIGNAL_CRC_R, data_type=c_uint8, data_count=6)
if result[0] >= ci.TSI_SUCCESS:
hdmi_crc = HdmiCrc.from_buffer(bytearray(result[1]))
stream_status.crc = [hdmi_crc.r, hdmi_crc.g, hdmi_crc.b]

17
UniTAP/dev/ports/modules/link/hdmi/status_tx.py
View File

@@ -1,7 +1,6 @@
from UniTAP.libs.lib_tsi.tsi_io import PortIO
from .types import HdmiModeTx, FrlMode, _update_error_counters_tx
from UniTAP.libs.lib_tsi.tsi_types import TSI_HDTX_FRL_STATUS_R, TSI_HDTX_CONTROL_W, TSI_HDTX_STATUS_R, \
TSI_HDTX_SINK_STATUS_R, TSI_HDTX_LANES_ERR_COUNTERS_R, TSI_HDTX_HPD_STATUS_R
import UniTAP.libs.lib_tsi.tsi_types as ci
from ctypes import c_uint32, c_uint64
@@ -19,10 +18,10 @@ class StatusTx:
self.__io = port_io
def __read_status(self) -> int:
return self.__io.get(TSI_HDTX_STATUS_R, c_uint32)[1]
return self.__io.get(ci.TSI_HDTX_STATUS_R, c_uint32)[1]
def __frl_status(self) -> FrlMode:
return FrlMode(self.__io.get(TSI_HDTX_FRL_STATUS_R, c_uint32)[1] & 0xF)
return FrlMode(self.__io.get(ci.TSI_HDTX_FRL_STATUS_R, c_uint32)[1] & 0xF)
@property
def video_status(self) -> bool:
@@ -42,7 +41,7 @@ class StatusTx:
Returns:
object of list type
"""
return _update_error_counters_tx(self.__io.get(TSI_HDTX_LANES_ERR_COUNTERS_R, c_uint64)[1])
return _update_error_counters_tx(self.__io.get(ci.TSI_HDTX_LANES_ERR_COUNTERS_R, c_uint64)[1])
@property
def channel_lock(self) -> list:
@@ -53,9 +52,9 @@ class StatusTx:
object of list type
"""
if self.__frl_status().Mode_Disable or self.hdmi_mode in [HdmiModeTx.HDMI_1_4, HdmiModeTx.HDMI_2_0]:
return self.__update_channel_lock(self.__io.get(TSI_HDTX_SINK_STATUS_R, c_uint32)[1], self.hdmi_mode)
return self.__update_channel_lock(self.__io.get(ci.TSI_HDTX_SINK_STATUS_R, c_uint32)[1], self.hdmi_mode)
else:
return self.__update_channel_lock(self.__io.get(TSI_HDTX_FRL_STATUS_R, c_uint32)[1], self.hdmi_mode)
return self.__update_channel_lock(self.__io.get(ci.TSI_HDTX_FRL_STATUS_R, c_uint32)[1], self.hdmi_mode)
@property
def hpd_status(self) -> bool:
@@ -65,7 +64,7 @@ class StatusTx:
Returns:
object of bool type
"""
return (self.__io.get(TSI_HDTX_HPD_STATUS_R, c_uint32)[1] & 0x1) != 0
return (self.__io.get(ci.TSI_HDTX_HPD_STATUS_R, c_uint32)[1] & 0x1) != 0
@property
def hdmi_mode(self) -> HdmiModeTx:
@@ -85,7 +84,7 @@ class StatusTx:
Args:
hdmi_mode (HdmiModeTx)
"""
self.__io.set(TSI_HDTX_CONTROL_W, hdmi_mode.value << 2, c_uint32)
self.__io.set(ci.TSI_HDTX_CONTROL_W, hdmi_mode.value << 2, c_uint32)
@property
def available_link_rate(self) -> float:

10
UniTAP/dev/ports/modules/link/hdmi/tmds_rx.py
View File

@@ -1,6 +1,6 @@
from UniTAP.libs.lib_tsi.tsi_io import PortIO
from .types import LinkMode
from UniTAP.libs.lib_tsi.tsi_types import TSI_HDRX_LINK_STATUS_R
import UniTAP.libs.lib_tsi.tsi_types as ci
from ctypes import c_uint32
@@ -17,7 +17,7 @@ class TmdsRx:
self.__input_stream_lock = False
def __read_link_status(self) -> int:
return self.__io.get(TSI_HDRX_LINK_STATUS_R, c_uint32)[1]
return self.__io.get(ci.TSI_HDRX_LINK_STATUS_R, c_uint32)[1]
@property
def clock_rate(self) -> int:
@@ -27,7 +27,7 @@ class TmdsRx:
Returns:
object of int type
"""
return 6 if self.__read_link_status() & 0x2 else 3
return 6 if self.__read_link_status() >> 1 & 0x1 else 3
@property
def link_mode(self) -> LinkMode:
@@ -37,7 +37,7 @@ class TmdsRx:
Returns:
object of `LinkMode` type
"""
self.__link_mode = LinkMode(self.__read_link_status() & 0x8)
self.__link_mode = LinkMode(self.__read_link_status() >> 3 & 0x1)
return self.__link_mode
@property
@@ -48,7 +48,7 @@ class TmdsRx:
Returns:
object of bool type
"""
self.__input_stream_lock = (self.__read_link_status() & 0x4) != 0
self.__input_stream_lock = (self.__read_link_status() >> 2 & 0x1) != 0
return self.__input_stream_lock
def __str__(self):

11
UniTAP/dev/ports/modules/link/hdmi/tmds_tx.py
View File

@@ -2,8 +2,7 @@ import warnings
from UniTAP.libs.lib_tsi.tsi_io import PortIO
from .types import ClockRate, LinkMode, ScramblerState
from UniTAP.libs.lib_tsi.tsi_types import TSI_HDTX_SINK_FEATURE_W, TSI_HDTX_STATUS_R, TSI_HDTX_SINK_STATUS_R, \
TSI_HDTX_CONTROL_W
import UniTAP.libs.lib_tsi.tsi_types as ci
from ctypes import c_uint32
@@ -21,13 +20,13 @@ class TmdsTx:
self.__scrambler = ScramblerState.Unknown
def __read_sink_status(self) -> int:
return self.__io.get(TSI_HDTX_SINK_STATUS_R, c_uint32)[1]
return self.__io.get(ci.TSI_HDTX_SINK_STATUS_R, c_uint32)[1]
def __read_hdtx_status(self) -> int:
return self.__io.get(TSI_HDTX_STATUS_R, c_uint32)[1]
return self.__io.get(ci.TSI_HDTX_STATUS_R, c_uint32)[1]
def __write_sink_feature(self, value: int):
self.__io.set(TSI_HDTX_SINK_FEATURE_W, value, c_uint32)
self.__io.set(ci.TSI_HDTX_SINK_FEATURE_W, value, c_uint32)
@property
def clock_rate(self) -> int:
@@ -71,7 +70,7 @@ class TmdsTx:
Args:
link_mode (LinkMode)
"""
self.__io.set(TSI_HDTX_CONTROL_W, link_mode.value, c_uint32)
self.__io.set(ci.TSI_HDTX_CONTROL_W, link_mode.value, c_uint32)
@property
def scrambler(self) -> bool: