132 lines
3.9 KiB
Python
132 lines
3.9 KiB
Python
from UniTAP.libs.lib_tsi.tsi import *
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from UniTAP.libs.lib_tsi.tsi_io import PortIO
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from .fec_shared import FECCounters
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from UniTAP.dev.ports.modules.dpcd.dpcd import DPCDRegisters
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class FecRx:
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"""
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Class `FecRx` allows working with FEC functionality from Sink (RX - receiver) side. You can:
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- Check capable FEC or not `is_capable`.
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- Check enabled FEC or not `is_enabled`.
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- Enable/Disable FEC `enable`.
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- Enable/Disable calculating sum of errors `aggregate_errors`.
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- Get error counters `get_error_counters`.
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- Clear all errors `clear`.
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"""
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def __init__(self, port_io: PortIO, dpcd: DPCDRegisters):
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self.__io = port_io
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self.__dpcd = dpcd
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self.__aggregate_error = 0
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def is_enabled(self) -> bool:
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"""
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Returns status of FEC, is enabled or not.
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Returns:
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object of `bool` type.
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"""
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result = self.__io.get(TSI_DPRX_FEC_STATUS_R, c_int)
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status_fec = ((result[1] & 0x1) != 0)
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return bool(status_fec)
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def is_capable(self) -> bool:
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"""
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Returns status of FEC, is capable or not.
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Returns:
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object of `bool` type.
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"""
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result = self.__io.get(TSI_DPRX_FEC_CTRL, c_int)
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enabled_fec = (result[1] & 0x1) != 0
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return enabled_fec
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def enable(self, enable: bool):
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"""
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Enable/Disable FEC.
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Args:
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enable (bool) - enable (True) or disable (False)
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"""
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val = 0x1 if enable else 0x0
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self.__io.set(TSI_DPRX_FEC_CTRL, val)
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def aggregate_errors(self, enable: bool):
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"""
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Enable/Disable calculating sum of errors.
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Args:
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enable (bool) - enable (True) or disable (False)
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"""
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result = self.__io.get(TSI_DPRX_FEC_CONTROL, c_int)
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val = result[1]
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if enable:
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val |= 0x2
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self.__aggregate_error = 1
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else:
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val &= ~0x2
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self.__aggregate_error = 0
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self.__io.set(TSI_DPRX_FEC_CONTROL, val)
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def get_error_counters(self) -> FECCounters:
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"""
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Get current error counters.
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Returns:
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object of `FECCounters` type
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"""
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result = FECCounters()
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lane_count = self.__io.get(TSI_R_DPRX_LINK_LANE_COUNT, c_int)[1]
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if lane_count == 4:
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lane_count += 1 if self.__aggregate_error else 0
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dpcd = self.__dpcd.read(0x120, 1).data[0]
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dpcdaggr = bool(dpcd & (1 << 6))
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for i in range(lane_count):
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if i == 0 and dpcdaggr:
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dpcd &= ~(1 << 6)
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if i == 4 and dpcdaggr:
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dpcd |= 1 << 6
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elif i == 4:
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continue
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if i < 4:
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dpcd &= ~(0x3 << 4)
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dpcd |= (i << 4)
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for j in range(1, 6):
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dpcd &= ~(0x7 << 1)
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v = dpcd | (j << 1)
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self.__dpcd.write(0x120, v)
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val = int.from_bytes(self.__dpcd.read(0x281, 2).data, 'little')
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if j == 1:
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result.uncorrectedBlockErrors[i] = val & 0x7FFF if val & 0x8000 else None
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elif j == 2:
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result.correctedBlockErrors[i] = val & 0x7FFF if val & 0x8000 else None
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elif j == 3:
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result.bitErrors[i] = val & 0x7FFF if val & 0x8000 else None
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elif j == 4:
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result.parityBlockErrors[i] = val & 0x7FFF if val & 0x8000 else None
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elif j == 5:
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result.parityBitErrors[i] = val & 0x7FFF if val & 0x8000 else None
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return result
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def clear(self):
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"""
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Clear all errors.
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"""
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address = 0x120
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dpcd = self.__dpcd.read(address, 1).data[0]
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old_fec = dpcd
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fec_ready = dpcd & ~0xE
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dpcd = fec_ready
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self.__dpcd.write(address, dpcd)
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dpcd = old_fec
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self.__dpcd.write(address, dpcd)
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