generic-acc.h 2.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106
  1. /*-------------------------------------------------------------------------
  2. *
  3. * generic-acc.h
  4. * Atomic operations support when using HPs acc on HPUX
  5. *
  6. * Portions Copyright (c) 1996-2016, PostgreSQL Global Development Group
  7. * Portions Copyright (c) 1994, Regents of the University of California
  8. *
  9. * NOTES:
  10. *
  11. * Documentation:
  12. * * inline assembly for Itanium-based HP-UX:
  13. * http://h21007.www2.hp.com/portal/download/files/unprot/Itanium/inline_assem_ERS.pdf
  14. * * Implementing Spinlocks on the Intel (R) Itanium (R) Architecture and PA-RISC
  15. * http://h21007.www2.hp.com/portal/download/files/unprot/itanium/spinlocks.pdf
  16. *
  17. * Itanium only supports a small set of numbers (6, -8, -4, -1, 1, 4, 8, 16)
  18. * for atomic add/sub, so we just implement everything but compare_exchange
  19. * via the compare_exchange fallbacks in atomics/generic.h.
  20. *
  21. * src/include/port/atomics/generic-acc.h
  22. *
  23. * -------------------------------------------------------------------------
  24. */
  25. #include <machine/sys/inline.h>
  26. #define pg_compiler_barrier_impl() _Asm_sched_fence()
  27. #if defined(HAVE_ATOMICS)
  28. /* IA64 always has 32/64 bit atomics */
  29. #define PG_HAVE_ATOMIC_U32_SUPPORT
  30. typedef struct pg_atomic_uint32
  31. {
  32. volatile uint32 value;
  33. } pg_atomic_uint32;
  34. #define PG_HAVE_ATOMIC_U64_SUPPORT
  35. typedef struct pg_atomic_uint64
  36. {
  37. /*
  38. * Alignment is guaranteed to be 64bit. Search for "Well-behaved
  39. * application restrictions" => "Data alignment and data sharing" on HP's
  40. * website. Unfortunately the URL doesn't seem to stable enough to
  41. * include.
  42. */
  43. volatile uint64 value;
  44. } pg_atomic_uint64;
  45. #define MINOR_FENCE (_Asm_fence) (_UP_CALL_FENCE | _UP_SYS_FENCE | \
  46. _DOWN_CALL_FENCE | _DOWN_SYS_FENCE )
  47. #define PG_HAVE_ATOMIC_COMPARE_EXCHANGE_U32
  48. static inline bool
  49. pg_atomic_compare_exchange_u32_impl(volatile pg_atomic_uint32 *ptr,
  50. uint32 *expected, uint32 newval)
  51. {
  52. bool ret;
  53. uint32 current;
  54. _Asm_mov_to_ar(_AREG_CCV, *expected, MINOR_FENCE);
  55. /*
  56. * We want a barrier, not just release/acquire semantics.
  57. */
  58. _Asm_mf();
  59. /*
  60. * Notes:
  61. * DOWN_MEM_FENCE | _UP_MEM_FENCE prevents reordering by the compiler
  62. */
  63. current = _Asm_cmpxchg(_SZ_W, /* word */
  64. _SEM_REL,
  65. &ptr->value,
  66. newval, _LDHINT_NONE,
  67. _DOWN_MEM_FENCE | _UP_MEM_FENCE);
  68. ret = current == *expected;
  69. *expected = current;
  70. return ret;
  71. }
  72. #define PG_HAVE_ATOMIC_COMPARE_EXCHANGE_U64
  73. static inline bool
  74. pg_atomic_compare_exchange_u64_impl(volatile pg_atomic_uint64 *ptr,
  75. uint64 *expected, uint64 newval)
  76. {
  77. bool ret;
  78. uint64 current;
  79. _Asm_mov_to_ar(_AREG_CCV, *expected, MINOR_FENCE);
  80. _Asm_mf();
  81. current = _Asm_cmpxchg(_SZ_D, /* doubleword */
  82. _SEM_REL,
  83. &ptr->value,
  84. newval, _LDHINT_NONE,
  85. _DOWN_MEM_FENCE | _UP_MEM_FENCE);
  86. ret = current == *expected;
  87. *expected = current;
  88. return ret;
  89. }
  90. #undef MINOR_FENCE
  91. #endif /* defined(HAVE_ATOMICS) */